The present invention relates to an integrated memory having a memory cell array with column lines and row lines. The cell array has memory cells, which are each connected to one of the row lines for selection of one of the memory cells and to one of the column lines for reading out or writing of a data signal. A row access controller is provided for activating one of the row lines for the selection of one of the memory cells and for controlling a deactivation operation for deactivating one of the row lines.
An integrated memory generally has a memory cell array containing the column lines and the row lines. The memory cells are in this case disposed at crossover points between the column lines and the row lines. For the selection of one of the memory cells, the latter are each connected to one of the row lines. To that end, by way of example, a selection transistor of respective memory cells is turned on by an activated row line, as a result of which a data signal of a corresponding selected memory cell can subsequently be read out or written. To that end, the selected memory cell is connected via the selection transistor to one of the column lines, via which the corresponding data signal is read out or written in.
In an inactive state, the row lines are usually deactivated, for example being precharged to a precharge potential or grounded. In other words, after the reading or writing of a data signal, the corresponding activated row line is deactivated by a deactivation operation. The deactivation operation and also the activation of one of the row lines for the selection of one of the memory cells are generally controlled by the row access controller.
In synchronous memories, in particular, such so-called SDRAMs or SGRAMs, the data processing speed is progressively increased owing to rising requirements by increasing the operating frequency (clock rate). As a result, the access time for an individual memory access is increasingly shortened. In this case, it must still be ensured that a defined minimum period of time is complied with in which a row line is to be activated for reading or writing a data signal. The minimum period of time is usually governed by physical constraints, for example by the length of the row line and the capacitive load connected therewith.
The minimum time in which a row line must remain open after a write operation in order to guarantee the memory cells are written to correctly is referred to as the so-called write recovery time. The time must be complied with in order that data cannot be lost during the write operation. In SDRAM or SGRAM memories, the write recovery time is usually a fixedly set time which is defined either as an analog time or as a time which is set in relation to a clock cycle. If a memory module is operated in a comparatively large frequency range, it can happen that, owing to a fixedly set write recovery time, the data throughput remains comparatively low even at a relatively high operating frequency of the memory.
It is accordingly an object of the invention to provide an integrated memory having a row access controller for activating and deactivating row lines which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has a comparatively high data throughput and is possible even at different operating frequencies of the integrated memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory. The memory contains a memory cell array having column lines, row lines, and memory cells. Each of the memory cells is connected to one of the row lines for selecting one of the memory cells and to one of the column lines for reading out or writing of a data signal. A row access controller is connected to the row lines for activating one of the row lines for the selecting one of the memory cells and for controlling a deactivation operation for deactivating one of the row lines. A signal terminal for a signal and a clock terminal for receiving a clock signal are provided. A control unit having a first input connected to the clock terminal and a second input connected to the signal terminal for receiving the signal, is provided. In an event of a read access to one of the memory cells, the signal defines a beginning of data outputting to a point outside the memory cell array. The data outputting is synchronized with the clock signal, and the signal is adjustable in dependence on an operating frequency of the integrated memory. The control unit has an output coupled to the row access controller and outputs an output signal for triggering the deactivation operation of one of the row lines after a write access to one of the memory cells.
The object is achieved by an integrated memory of the type mentioned in the introduction having a control unit containing an input, which is connected to a signal terminal for a signal that, in the event of a read access to one of the memory cells, defines the beginning of data outputting to a point outside the memory cell array. The data outputting is synchronized with a clock signal, the signal being adjustable depending on an operating frequency of the memory, and an output, which is connected to the row access controller, for outputting an output signal for triggering the deactivation operation of one of the row lines after a write access to one of the memory cells.
The control unit makes it possible to set the write recovery time to depend on the operating frequency of the memory. As a result, this is defined as a frequency-dependent time variable and set accordingly by the control unit. As a result, the write recovery time can be optimized to the operating frequency, so that a comparatively high data throughput can be achieved even at different operating frequencies. As soon as the write recovery time has elapsed after a write access to one of the memory cells, the deactivation operation of the relevant row line is triggered by the output signal of the control unit.
In this case, the write recovery time is determined in a manner dependent on a so-called CAS latency signal. The signal indicates when synchronized data output to a point outside the memory cell array begins in the event of a read access to one of the memory cells. As a result, in the event of a read access, a data packet is obtained on a column line at a defined point in time. In synchronous memory modules, the CAS latency signal is usually programmed by a so-called mode register set command. In this case, the CAS latency signal is programmed and set depending on the operating frequency of the memory, in order to obtain an optimum data throughput at every operating frequency in the event of a read access to one of the memory cells. The signal is therefore suitable for drawing conclusions about the frequency range of the memory, and for being utilized for determining the write recovery time for a write access to one of the memory cells. This can be set in the control unit in a matching manner with respect to the operating frequency using the programmed CAS latency signal. The deactivation operation of one of the row lines is accordingly initiated by the output signal of the control unit.
In one embodiment of the invention, the control unit is connected to a terminal for the clock signal. The output signal of the control unit is derived from the clock signal, an instant of a switching edge of the output signal being defined, by the control unit, depending on the state of the CAS latency signal present at the input.
To that end, the control unit advantageously has a delay circuit, by which the clock signal can be delayed by one or more clock periods and can be output as an output signal. The triggering of the deactivation operation of one of the row lines is accordingly delayed by one or more clock periods of the clock signal by the delay circuit, thereby complying with the write recovery time.
The number of clock periods to be delayed can be set in a discrete manner, for example. To that end, the control unit advantageously has a selection circuit, which is connected to the delay circuit and to the input of the control unit. In this case, the number of clock periods to be delayed is set in the selection circuit by the CAS latency signal present at the input of the control unit. The selection circuit is connected to the delay circuit, which performs the corresponding delay of the clock signal depending on the output signal of the selection circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having a row access controller for activating and deactivating row lines, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.